The present invention relates generally to data processing circuitry; and, more particularly, it relates to a method of addressing a particular location of a memory organized into words having three partitions.
In most types of data processing systems, memory is provided to store data and instructions for use by processing circuitry. When processing circuitry (e.g., a processor core) needs to write data into or read data out of an external memory location, an address is generated for the data and placed on an address bus. The address is typically generated by an addressing unit of the data processing circuitry, and frequently specifies a particular group of bits within a memory partition.
Address translation circuitry may be utilized to convert an address provided to or received from an addressing unit to an address used by a direct memory access (DMA) controller/memory controller to access the physical memory space. Corresponding data is then driven on a data bus or system bus during a data cycle. Operation of the address translation circuitry is typically transparent to the processing circuitry.
Memory may be organized in many ways, including physical or logical partitions of varying widths and depths. Consequently, many different addressing schemes are employed. In one common memory architecture, the addressing mechanism generates a binary address for a specific byte. This address may then be translated or mapped to the physical location of the byte in memory. If the memory is organized into partitions of two- or four-byte words, address mapping is relatively straightforward. More particularly, in the case of a memory having a four byte depth, the last two bits of the address identify a particular one of four bytes at a given double-word address. Similarly, in a memory having a two byte depth, only one bit is needed to identify a particular byte.
For various reasons, it may be desirable to organize memory into xe2x80x9cwordsxe2x80x9d having an odd number of partitions. For example, a memory can be organized into words having three partitions in order to provide improved bandwidth over a smaller number of partitions, or to eliminate packaging or board costs associated with a greater number of partitions. The classic approach to address translation, if applied to address generation in such a system, is not effective. For at least this reason, odd numbers of memory partitions have largely been avoided in prior systems.
Briefly, the present invention relates to a method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) of partitions. The method permits, for example, efficient translation of a byte address into a word address and byte offset value. The method provides greater flexibility in the organization of memory, thereby permitting designers to optimize memory system designs according to bandwidth requirements and other constraints.
Upon receiving an address for a particular memory location, address translation circuitry according to the present invention effectively converts the address to a floating point number. The address translation circuitry then divides the received address by three to determine which word of memoryxe2x80x94and which bytexe2x80x94is being addressed. In particular, the quotient of the division process provides the word address, while the remainder provides the byte offset. Memory addressed by the present invention may be organized into xe2x80x9cwordsxe2x80x9d of varying length. For example, each xe2x80x9cwordxe2x80x9d may be ninety-six bits wide, with partitions of thirty-two bits each. In this embodiment, the remainder of the division process identifies a particular thirty-two bit partition.
The address translation circuitry performs the division by three operation by multiplying the floating point number by a binary value of approximately one third (0.010101 . . . ). The binary multiplication process involves shifting and adding of the floating point number. Shifting of the floating point number is equivalent to selecting different portions of the received address for addition.
In one embodiment of the invention, bits are added to the received address to increase the precision of the division operation such that the fractional result will settle to one of 0.000 . . . , 0.0101 . . . or 0.1010 . . . binary. In this embodiment, the two most significant bits of the fractional portion of the result equal the required byte offset (e.g., 0=00 binary; 1=01 binary and 2=10 binary). The integer portion of the result is the translated word address.
The byte address may be stored in registers and shifted left by two bits at a time to perform the division operation. However, shifting/division using registers or other sequential logic requires at least one clock cycle per two bits of address. Depending on the size of the address bus, the translation process may thus consume several clock cycles. Accordingly, in one embodiment of the invention the division process is carried out by combinational logic (i.e., logic that is not clocked). In this manner, address translation may be completed in as few as a single clock cycle.